====== [hemmerling] Electronic Design Automation ( EDA ) 3/5 - Design for Application-Specific Integrated Circuits ( ASIC ) - Design of digital Chips ======
Related pages:
  *[[altera.html|Altera "System on Chip" ( SoC )]].
  *[[eda01.html|Electronic Design Automation ( EDA ) 1/5 - Installation Engineering]].
  *[[eda02.html|Electronic Design Automation ( EDA ) 2/5 - Schematics Capture, Schematics Simulation and PCB Design]].
  *[[eda04.html|Electronic Design Automation ( EDA ) 4/5 - Design for Application-Specific Integrated Circuits ( ASIC ) - Design of analog Chips]].
  *[[eda05.html|Electronic Design Automation ( EDA ) 5/5 - Design for Application-Specific Integrated Circuits ( ASIC ) - A simple Frequency Divider]].
  *[[electronics01.html|Electric Units & Electronics 1/3 - My Electronics, Electronics Workbench Equipment, Electronics Literature & Resources]].
  *[[electronics02.html|Electric Units & Electronics 2/3 - Actors, Sensors, Embedded Systems Electronics and suitable Control Systems]].
  *[[electronics03.html|Electric Units & Electronics 3/3 - Manufacturers, Distributors, Vendors & Datasheets]].
===== FPGA Chip Design Languages =====
==== Low-Level descriptive parallel Modelling ====
Though the code looks like "Pascal" or "C", it is not executed in this way.
=== MyHDL ====
  *[[http://www.myhdl.org/|MyHDL]].
  *[[http://www.twitter.com/MyHDL|Twitter "MyHDL"]].
  *[[http://en.wikipedia.org/wiki/MyHDL|EN.Wikipedia "MyHDL"]].
=== PSHDL ( Plain Simple Hardware Description Language ) ====
  *[[http://www.pshdl.org/|PSHDL Online]] - "Download library" -> "pshdl_pkg.vhd".
    *Blog [[http://blog.pshdl.org/|PSHDL Language. A blog about the development of PSHDL, the Plain & Simple Hardware Description Language and multiple rants about the shortcomings of VHDL and Verilog]].
    *[[http://www.pshdl.org/pshdltutorial.html|PSHDL Tutorial - Getting started with PSHDL]].
    *[[http://www.pshdl.org/pshdl.html|PSHDL Language Description]].
    *[[http://www.pshdl.org/101/index.html|PSHDL "FPGA 101 Tools and files"]].
    *[[http://www.pshdl.org/101/|PSHDL file directory "101"]].
    *[[http://dart.pshdl.org/out/pshdl.html/|PSHDL Online compiler]].
    *[[http://boards.pshdl.org/|PSHDL Board info page]].
  *Main developer: Karsten Becker, [[http://www.xing.com/profiles/Karsten_Becker40|XING "Karsten Becker"]].
  *[[http://www.twitter.com/PSHDL|Twitter "PSHDL"]].
  *To work with PSHDL on the FPGA board [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm| Xilinx Inc "Avnet Spartan-6 LX9 MicroBoard"]], you need the free [[http://www.xilinx.com/products/design-tools/ise-design-suite/|Xilinx ISE Design Suite: WebPACK Edition]] and install the download library "pshdl_pkg.vhd".
=== PSL ( Property Specification Language ) ====
  *[[http://en.wikipedia.org/wiki/Property_Specification_Language|EN.Wikipedia "Property Specification Language"]] ( PSL ).
=== Verilog & SystemVerilog ===
== Literature ==
  *Book [[http://www.amazon.de/exec/obidos/ASIN/1546776346/hemmerling-21|Stuart Sutherland "RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design"]].
  *Book [[http://www.amazon.de/exec/obidos/ASIN/0983497303/hemmerling-21|Blaine Readler "Verilog by Example: A Concise Introduction for FPGA Design"]].
== Resources ==
  *[[http://en.wikipedia.org/wiki/Verilog|EN.Wikipedia "Verilog"]], [[http://de.wikipedia.org/wiki/Verilog|DE.Wikipedia "Verilog"]].
  *[[http://en.wikipedia.org/wiki/SystemVerilog|EN.Wikipedia "SystemVerilog"]].
=== VHDL ===
== Dataflow Paradigm ==
  *Traditional RTL.
    *[[http://en.wikipedia.org/wiki/Register-transfer_level|EN.Wikipedia "Register-transfer level"]], [[http://de.wikipedia.org/wiki/Registertransferebene|DE.Wikipedia "Registertransferebene"]].
== Behavioral Paradigm ==
  *[[http://www.edn.com/behavioral-modeling-in-vhdl-simulation/|EDN "Behavioral modeling in VHDL simulation"]].
  *[[http://www.people.vcu.edu/~rhklenke/tutorials/vhdl/|Dr. Robert H. Klenke "Tutorial for VHDL Simulation with ModelSim and QSPro"]].
    *[[http://www.people.vcu.edu/~rhklenke/tutorials/vhdl/modules/m12_23/sld006.htm|Dr. Robert H. Klenke "Example Behavioral VHDL Model"]].
== Dataflow Paradigm versus Behavioral Paradigm ==
  *[[http://www.quora.com/What-exactly-is-the-difference-between-the-dataflow-and-behavioral-paradigms-in-VHDL|Quora "What exactly is the difference between the dataflow and behavioral paradigms in VHDL?"]].
  *[[http://www.stackoverflow.com/questions/18682019/confusion-between-behavioural-and-dataflow-model-programs-in-vhdl|StackOverflow "Confusion between Behavioural and Dataflow model Programs in VHDL"]].
== Literature ==
  *[[http://www.ashenden.com.au/|Peter Ashenden "Ashenden Designs"]] - Autor of books about VHDL design.
  *Book [[http://www.amazon.de/exec/obidos/ASIN/0970539428/hemmerling-21|Ben Cohen: "Real Chip Design and Verfication Using Verilog and VHDL"]] - The accompanying CD is filled with many free VHDL sources.
  *Book [[http://www.amazon.de/exec/obidos/ASIN/0471899720/hemmerling-21|Ulrich Heinkel, Martin Padeffke, Werner Haas, Thomas Buerner, Herbert Braisz, Thomas Gentner, Alexander Grassmann "The VHDL Reference: A Practical Guide to Computer-Aided Integrated Circuit Design including VHDL-AMS"]].
  *[[http://www.csee.umbc.edu/portal/help/|University of Maryland Baltimore County, Computer Science and Electrical Engineering Department, CSEE HELP pages]].
    *[[http://www.csee.umbc.edu/portal/help/VHDL/|University of Maryland Baltimore County, Computer Science and Electrical Engineering Department, CSEE HELP pages "VHDL reference material"]].
      *[[http://www.csee.umbc.edu/portal/help/VHDL/numeric_std.vhdl|University of Maryland Baltimore County, Computer Science and Electrical Engineering Department, CSEE HELP pages "Standard VHDL Synthesis Package (1076.3, NUMERIC_STD)"]].
  *Book [[http://www.amazon.de/exec/obidos/ASIN/3486716778/hemmerling-21|Jürgen Reichardt, Bernd Schwarz: "VHDL-Synthese: Entwurf digitaler Schaltungen und Systeme"]].
    *The accompanying website [[http://users.etech.haw-hamburg.de/users/Reichardt/buch.html|Reichardt Schwarz VHDL Synthese Synthesis]] with a free HTML online book edition.
== Resources ==
  *[[http://en.wikipedia.org/wiki/VHDL|EN.Wikipedia "VHDL"]], [[http://de.wikipedia.org/wiki/Very_High_Speed_Integrated_Circuit_Hardware_Description_Language|DE.Wikipedia "Very High Speed Integrated Circuit Hardware Description Language"]].
==== High-level imperative sequential Modelling - "FPGA Accelleration for Software Programmers" ====
The code looks like "C/C++" and is executed in this way.
=== CUDA & SYCL ===
== CUDA ==
  *Experts told me what is OpenCL for ALTERA, is the software framework of CUDA for NVIDIA. You may create "CUDA Applications" for NVIDIA ( graphics card ) platforms.
  *[[http://developer.nvidia.com/cuda-toolkit|NVIDIA Developer "CUDA Toolkit"]].
  *[[http://en.wikipedia.org/wiki/CUDA|EN.Wikipedia "CUDA"]], [[http://en.wikipedia.org/wiki/CUDA|EN.Wikipedia "CUDA"]].
== SYCL ==
  *[[http://www.khronos.org/sycl/|The Khronos Group Inc. "SYCL"]].
  *[[http://developer.codeplay.com/|Codeplay Developer]] - "Download the latest releases from Codeplay to develop with OpenCL and SYCL on a range of different hardware, browse our guides, read API reference material and follow our tutorials".
  *[[http://developer.codeplay.com/products/computecpp/ce/2.11.0/guides/sycl-for-cuda-developers|Codeplay Developer "SYCL For CUDA Developers"]].
  *[[http://en.wikipedia.org/wiki/SYCL|EN.Wikipedia "SYCL"]].
=== Java ===
=== OpenCL ===
== OpenCL by ALTERA ==
  *[[http://www.altera.com/products/design-software/embedded-software-developers/opencl/overview.html|ALTERA "Altera SDK for OpenCL"]].
    *[[http://www.altera.com/support/support-resources/design-examples/design-software/opencl.html|ALTERA "OpenCL Design Examples"]].
      *[[http://www.altera.com/support/support-resources/design-examples/design-software/opencl/hello-world.html|ALTERA "Hello World Design Example"]].
    *Webcast [[http://www.altera.com/webcasts/opencl-overview/presentation.html|ALTERA "Introduction to FPGA Accelleration for Software Programmers using OpenCL"]].
  *[[http://dl.altera.com/opencl/|ALTERA Download Center "Altera SDK for OpenCL"]].
== OpenCL by AMD ( formerly: ATI ) ==
  *[[http://developer.amd.com/tools-and-sdks/opencl-zone/|AMD Developer Central "OpenCL Zone - Accelerate Your Applications]].
    *[[http://developer.amd.com/tools-and-sdks/opencl-zone/opencl-resources/programming-in-opencl/porting-cuda-applications-to-opencl/|AMD Developer Central "OpenCL Zone - Accelerate Your Applications" - "Porting CUDA Applications to OpenCL"]].
== Tutorials, Sample Code & Addon Frameworks ==
  *[[http://developer.apple.com/library/mac/samplecode/OpenCL_Hello_World_Example/Listings/hello_c.html|Apple Developers, Mac Developer Library "OpenCL Hello World Example"]].
  *[[http://blogger.ivanceras.com/2013/03/a-working-opencl-sample-for-nvidia.html|Digital Wizard Apprentice
Aspirant little steps towards understanding the mystery of programming and digital "A working OpenCL sample for NVIDIA graphics card on Linux"]].
  *[[http://www.dhruba.name/2012/08/21/opencl-cookbook-series-reference/|Dhruba Bandopadhyay. Maximum Zeal ~ Emphatic prose on indulged fascinations "OpenCL Cookbook: Series Reference"]].
  *[[http://code.google.com/p/simple-opencl/|Google Code "simple-opencl. SimpleOpenCL is a library created to reduce the amount of host code needed to write an OpenCL program"]].
  *[[http://www.computer-graphics.se/hello-world-for-cuda.html|Ingemar Ragnemalm, Computer Graphics.se "The real 'Hello World!' for CUDA, OpenCL and GLSL!"]] #.
== Resources ==
  *"FPGA Board Support Packages" ( BSP ) are an important aspect of the "business model" of the FPGA industry. BSPs are not "free" but usually require a license. Usually, a valid BSP license file must be attached to the OpenCL compiler chain, to enable its operation for a specific board target.
  *[[http://www.alteraboards.com/|BittWare FPGA Platforms]].
    *[[http://www.alteraboards.com/product/opencl-developers-bundle/|BittWare FPGA Platforms "OpenCL Developer’s Bundle. Arria 10 or Stratix V FPGA-based PCIe Board and Development Tools for OpenCL"]].
    *[[http://www.alteraboards.com/product/opencl-board-support-packages-bsps/|BittWare FPGA Platforms "OpenCL Board Support Packages (BSPs)"]] - "FPGA Board Support Packages for the Altera OpenCL SDK".
  *[[http://www.stackoverflow.com/questions/tagged/opencl|StackOverflow - Tagged Questions "opencl"]].
=== SystemC ===
  *The free SystemC modeling IDE [[http://www.eda.ir/|Electronics Design Automation "SystemC_Win"]] for use with Borland C++ 5.5, on Windows. 
    *[[http://web.archive.org/web/*/http://www.geocities.com/systemc_win/|Archive.org "Geocities 'SystemC_Win'"]] ( - 2009-10-25 ) - Download of the source code of the legacy version "SystemC_Win Version 1.0 Beta".
  *[[http://www.systemc.org/|Open SystemC Initiative (OSCI)]].
  *[[http://en.wikipedia.org/wiki/SystemC|EN.Wikipedia "SystemC"]], [[http://de.wikipedia.org/wiki/SystemC|DE.Wikipedia "SystemC"]].
  *[[http://en.wikipedia.org/wiki/Accellera|EN.Wikipedia "Accellera"]] - "Open SystemC Initiative".
=== SystemRDL ===
== Specification ==
  *[[http://www.accellera.org/downloads/standards/systemrdl|Accellera Systems Initiative]] - "Download SystemRDL" ( specification ).
== Resources ==
  *[[http://www.agnisys.com/products/ids40/systemrdl/|Agnisys, Inc. "Nest Generation SystemRDL. Using IDesignSpec for register implementation"]].
  *[[http://www.design-reuse.com/news/13462/denali-opens-register-description-language-systemrdl.html|Design & Reuse "
Denali Opens Register Description Language, Announces SystemRDL"]], 2006-05-30.
  *[[http://www.vmmcentral.org/vmartialarts/2011/07/the-one-stop-shop-get-done-with-everything-you-need-to-do-with-your-registers/index.html|VMM Central, Verification Martial Arts: A Verification Methodology Blog "The One stop shop: get done with everything you need to do with your registers"]] - "we use SystemRDL".
  *[[http://en.wikipedia.org/wiki/SystemRDL|EN.Wikipedia "SystemRDL"]].
  *[[http://en.wikipedia.org/wiki/Cadence_Design_Systems|EN.Wikipedia "Cadence Design Systems"]], [[http://de.wikipedia.org/wiki/Cadence_Design_Systems|DE.Wikipedia "Cadence Design Systems"]].
===== FPGA Chip Manufacturers & its free FPGA Design Tools =====
==== Allwinner Technology ====
  *[[http://fr.wikipedia.org/wiki/Allwinner_A80|FR.Wikipedia "Allwinner A80"]].
  *[[http://en.wikipedia.org/wiki/Allwinner_Technology|EN.Wikipedia "Allwinner Technology"]], [[http://de.wikipedia.org/wiki/Allwinner_Technology|DE.Wikipedia "Allwinner Technology"]]. 
==== ALTERA ====
  *See [[altera.html|Altera "System on Chip" ( SoC )]].
==== Efinix ====
  *[[https://www.efinixinc.com/|Efinix, Inc.]].
  *Distributor [[http://www.trs-star.com/|TRS-STAR GmbH]] - First contact in 2022-12.
    *[[http://www.xing.com/pages/trs-star-gmbh|XING "TRS-Star GmbH"]].
    *[[http://www.linkedin.com/company/trs-star/|LinkedIn "TRS-STAR GmbH"]].
    *[[http://www.linkedin.com/in/werner-geiger-407a0621a/|LinkedIn "Werner Geiger"]].
==== GOWIN Semiconductor Corp. ====
=== The Company & it's FPGA Chips ===
  *[[http://www.gowinsemi.com/en/|GOWIN Semiconductor Corp.]].
=== Design Tool "GOWIN EDA" ===
  *[[http://www.gowinsemi.com.cn/faq.aspx|GOWIN Semiconductor Corp. "FAQ"]] - GOWIN EDA Download.
=== Resources ===
  *Remote Chaos Experience ( RC3 ), 2020-12-2i: Speech "How to fuzz an FPGA – My experience documenting Gowin FPGAs" by Pepijn de Vos.
  *[[http://www.eevblog.com/forum/fpga/gowin-fpga/|EEVblog Electronics Community Forum "GOWIN FPGA"]].
  *[[http://github.com/abhra0897/gowin-easy-linux|GitHub "abhra0897/gowin-easy-linux"]] - "Easy setup of GoWin FPGA SDK on Linux. A single script (main_launcher) automates all the critical steps and quickly fires up the IDE".
  *[[http://www.medium.com/coinmonks/program-your-first-fpga-with-gowin-gw1n-4-b0d5c22b9fea|Medium "Program Your First FPGA With GOWIN GW1N-4"]].
  *[[http://www.reddit.com/r/FPGA/comments/dx8yut/gowin_ide_has_anyone_managed_to_use_it/|Reddit "Gowin IDE - has anyone managed to use it ?"]].
  *[[http://tangnano.sipeed.com/en/get_started/install-the-ide.html|Tang Nano DOC "IDE installation"]].
==== Lattice Semiconductor ====
=== The Company & it's FPGA Chips ===
  *[[http://www.latticesemi.com/|Lattice Semiconductor]].
  *[[http://www.latticesemi.com/en/Products/FPGAandCPLD.aspx|Lattice Semiconductor "FPGAs & CPLDs"]].
  *[[http://en.wikipedia.org/wiki/Lattice_Semiconductor|EN.Wikipedia "Lattice Semiconductor"]], [[http://de.wikipedia.org/wiki/Lattice_Semiconductor_Corporation|DE.Wikipedia "Lattice Semiconductor Corporation"]].
=== Design Tools ===
  *[[http://www.latticesemi.com/Products/DesignSoftwareAndIP.aspx|Lattice Semiconductor "Design Software & IP"]].
=== Training ===
  *[[http://www.lec2-fpga.com/|LEC2 - Lattice Education Competence Center]].
==== Microsemi Corporation, a Microchip Company ( formerly: Actel ) ====
=== The Company & it's FPGA Chips ===
  *[[http://www.microsemi.com/|Microsemi Corporation, a Microchip Company]] ( formerly: Actel ).
  *[[http://www.microsemi.com/products/fpga-soc/fpga-and-soc|Microsemi Corporation "FPGA & SoC"]].
  *[[http://en.wikipedia.org/wiki/Actel|EN.Wikipedia "Actel"]], [[http://de.wikipedia.org/wiki/Actel|DE.Wikipedia "Actel"]].
  *[[http://en.wikipedia.org/wiki/Microsemi|EN.Wikipedia "Microsemi"]], [[http://de.wikipedia.org/wiki/Microsemi|DE.Wikipedia "Microsemi"]].
=== Actel ===
  *[[http://www.actel.com/products/smartfusion/|Microsemi Corporation / Actel "SmartFusion"]].
  *[[http://www.actel.com/Portal/|Microsemi Corporation / Actel - Consumer Portal]], [[https://soc.microsemi.com/Portal/|Microsemi SoC Customer Portal]].
=== Firmware, IP Cores ===
  *[[http://www.microsemi.com/product-directory/design-resources/5092-ip-cores|Microsemi Corporation "FPGA Intellectual Property Cores"]].
  *[[http://www.microsemi.com/product-directory/design-tools/4880-firmware-catalog|Microsemi Corporation "Firmware Catalog"]].
    *"Note: You do not need to install Firmware Catalog if you have already installed, or plan to install, Libero software. Firmware Catalog is included with Libero software installation".
    *"The Firmware Catalog notifies the user if new firmware cores or firmware updates are available from Microsemi's web repository. The updates can be downloaded into a local vault on a PC".
=== Design Tools ===
  *The free Eclipse-based IDE [[http://www.microsemi.com/product-directory/design-tools/4879-softconsole|Microsemi Corporation "SoftConsole"]] - "SoftConsole is Microsemi’s free software development environment facilitating the rapid development of bare-metal and RTOS based C/C++ software for Microsemi CPU and SoC based FPGAs. It provides development and debug support for all Microsemi SoC FPGAs and 32-bit soft IP CPUs".
  *[[http://www.microsemi.com/products/fpga-soc/design-resources/design-software/libero-soc|Microsemi Corporation "Libero SoC"]].
    *"**Important Note: For users working offline with Libero SoC v12.4, [[http://soc.microsemi.com/download/reg/download.aspx?p=f=LiberoSoC_v12_5_MEGAVAULT_WIN|Microsemi "Download Libero SoC v12.5 Mega Vault (ZIP)"]] or [[http://soc.microsemi.com/download/reg/download.aspx?p=f=LiberoSoC_v12_4_MEGAVAULT_LIN|Download Libero SoC v12.4 Mega Vault (Linux)(BIN)]] has to be installed**".
    *[[http://soc.microsemi.com/Portal/|Microsemi "Microsemi SoC Licensing"]] - "To obtain a FREE Libero Evaluation or Silver license, click the button below".
      *Free 1 Year Licenses ( 2020-09: "The following Evaluation and Silver licenses support Libero SoC PolarFire, Libero SoC v11.8, and above versions only" ):
        *Libero SoC v12.5 is the first version with PolarFire SoC support :-)!
        *Libero Silver 1 Year Floating License for Windows/Linux.
        *Libero Silver 1 Year Node-lock License for Windows => "Disk ID".
        *Synopsys Synphony Model Compiler ME. Requires MATLAB/Simulink from Mathworks.
      *<del>PolarFire Seminar license for Windows PC ( 15-days trial )</del>.
    *[[http://www.microsemi.com/products/fpga-soc/design-resources/licensing|Microsemi "Licensing"]].
      *"Libero Silver, Evaluation, Gold, Platinum, and Standalone licenses. Libero Silver and Evaluation are FREE licenses that support most devices as shown in the following tables. All licenses serve Libero SoC PolarFire, Libero SoC and Libero IDE".
      *On this HTML page, a table is published which explains the "Software License Requirements", in detail.
    *In 2020, due to Corona, you may apply at [[http://soc.microsemi.com/Portal/|Microsemi "Microsemi SoC Licensing"]] for a 60-days trial licenses.
    *[[http://soc.microsemi.com/Portal/SLRSPages/Controls/DISKIDinstruction.htm|Microsemi "How to obtain a Disk ID"]]. If you apply for a free workshop, you must name your "Disk ID" to get a free license. On Windows, open a command shell ( COMMAND.COM, CMD.COM ), and type "Vol C:". 
  *For my 1.st fat Win64 development notebook, I got:
<code>
C:\Users\Administrator>vol c:
 Datenträger in Laufwerk C: ist WIN1
 Volumeseriennummer: B6B0-3DA2
</code>
  *For my 2.nd fat Win64 development notebook, I got:
<code>
C:\Users\Administrator>vol c:
 Datenträger in Laufwerk C: ist WIN1
 Volumeseriennummer: 90E2-CAD4
</code>
=== Hands-on Workshop "PolarFire FPGA Workshop", 2018-01-18 ===
  *PolarFire v2.0 IDE.
    *[[http://www.microsemi.com/products/fpga-soc/design-resources/design-software/libero-soc-polarfire#downloads|Microsemi "Libero SoC PolarFire"]].
    *You need to apply at [[http://soc.microsemi.com/Portal/|Microsemi "Microsemi SoC Licensing"]] for a 15-days trial "PolarFire Seminar license for Windows PC".
    *"Important Notes: For users working offline with Libero SoC PolarFire v2.0, [[http://soc.microsemi.com/download/reg/download.aspx?p=f=LiberoSoC_PolarFire_v2_MEGA_VAULT|Libero SoC PolarFire v2.0 MegaVault]] has to be installed". The vault ist the database with all FPGA IP cores. The default installation place is "C:\microsemi\commons\vault".
  *[[http://www.arrow.com/en/products/everest-dev-board/arrow-development-tools|Arrow "EVEREST-DEV-BOARD"]] - "MPF300TS-1FCG1152I FPGA Evaluation Board 3GB RAM 128MB/128MB SPI Flash".
=== Hands-on Online Workshops 2020 "Libero SoC Flash-FPGA Workshop" & "SoftConsole MCU Workshop" ===
  *[[http://www.arrow.de/to-go-dach-seminars|Arrow Electronics, Inc. "Arrow To Go - Webinare für die DACH Region"]].
  *[[http://www.arrow.com/en/microchip-fpga#6-webinars|Arrow Electronics, Inc. "Microchip FPGA"]].
    *"Libero SoC Flash-FPGA Workshop", 2020-10-06, 14:00 - 16:00 CET.
      *My [[http://global.gotowebinar.com/join/368074021206561806/927988539|GotoWebinar Recording "Libero SoC Flash-FPGA Workshop, 2020-10-06"]].
    *"SoftConsole MCU Workshop”, 2020-11-04, 09:00 - 11:00 CET.
      *My GotoWebinar "SoftConsole MCU Workshop, 2020-11-04" ( no recording :-( ).
      *[[ftp://ftpsoc.microsemi.com/outgoing/Solution_SMF2000-M3_BaseDesign_L12d5_SC6d4_20201104_0744.zip|Solution_SMF2000-M3_BaseDesign_L12d5_SC6d4_20201104_0744.zip]].
      *[[http://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga|Microsemi "PolarFire SoC"]] - "Renode provides a simulation model for PolarFire SoC and Mi-V soft-CPUs and can be used to debug firmware. Renode is bundled with SoftConsole v6.x and can be downloaded for free".
        *[[http://www.renode.io/|Renode]] - "An open source software development framework with commercial support from Antmicro that lets you develop, debug and test multi-node device systems reliably, scalably and effectively".
        *At "C:\Microchip\SoftConsole-v6.4\extras\workspace.examples" ( not "C:\Microsemi\.." ), Renote configurations are included with Softconsole.
    *Free 1 Year Licenses are ok for the workshop:
      *Libero Silver 1 Year Floating License for Windows/Linux.
      *Libero Silver 1 Year Node-lock License for Windows.
=== My TEM0001 Boards shipped with a "SmartFusion2 SoC FPGA", by Trenz Electronic GmbH ===
  *[[http://www.trenz.org/|Trenz Electronic GmbH]].
  *Wiki [[http://wiki.trenz-electronic.de/|Trenz Electronic GmbH Wiki]].
  *My TEM0001 boards were a gift given Microsemi on their hands-on workshops.
    *Workshop dates:
      -2018-01-18.
      -2020-10-06 and 2020-11-04.
    *[[http://www.trenz.org/smf2000-info|Trenz Electronic GmbH "TEM0001 - Resources. TEM0001 2.5 x 6.15 cm SoC module with MicroSemi SmartFusion2 SoC FPGA"]], [[http://wiki.trenz-electronic.de/display/PD/TEM0001+Resources|Trenz Electronic GmbH "TEM0001 - Resources. TEM0001 2.5 x 6.15 cm SoC module with MicroSemi SmartFusion2 SoC FPGA"]].
    *[[http://shop.trenz-electronic.de/de/TEM0001-01A-010C-SMF2000-FPGA-Modul-mit-Microsemi-SmartFusion2-8-MByte-SDRAM|Trenz Electronic GmbH "SMF2000 FPGA-Modul mit Microsemi SmartFusion2, 8 MByte SDRAM"]].
    *[[http://www.arrow.com/en/products/smf2000/trenz-electronic-gmbh|Arrow "SMF2000 - Trenz Electronic GmbH"]].
  *[[http://www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion2|Microsemi "SmartFusion2 SoC FPGA Family"]].
  *Experts told me, that you need the wiring diagram of the board, if you want to understand the IO constraints.
==== Xilinx ====
  *See  [[xilinx.html|Xilinx "System on Chip" ( SoC )]].
==== Some other FPGA Chip Manufacturerers ====
  *[[http://www.quicklogic.com/| QuickLogic Corp]] - "Customer Specific Standard Products ( CSSPs ), Customizable Semiconductors for Mobile Devices".
    *[[http://www.quicklogic.com/support/development-tools/software/quickworks/|QuickLogic Corp "QuickWorks"]] - QuickLogic provides a complete design environment for Field Programmable Gate Array (FPGA) designs".
===== Some other commercial EDA Tools =====
  *[[http://www.aldec.com/|Aldec, Inc]] - "The Design Verification Company".
    *[[http://en.wikipedia.org/wiki/Aldec|EN.Wikipedia "Aldec]].
  *[[http://www.altium.com/|Altium]].
    *[[http://www.altium.com/en/products/altium-designer|Altium Designer]].
      *[[http://en.wikipedia.org/wiki/Altium_Designer|EN.Wikipedia "Altium Designer"]], [[http://de.wikipedia.org/wiki/Altium_Designer|DE.Wikipedia "Altium Designer"]] - "Schematic capture, PCB design,  FPGA and embedded software tools, Release/data management".
  *[[http://www.mentor.com/|Mentor Graphics]].
    *[[http://www.model.com/|Mentor Graphics "Model Sim"]] - "HDL Simulation", "Unified debug environment for Verilog, VHDL, and SystemC".
      *The free [[http://www.mentor.com/company/higher_ed/modelsim-student-edition|Mentor Graphics "ModelSim PE Student Edition"]].
      *The free [[http://www.altera.com/products/software/quartus-ii/modelsim/qts-modelsim-index.html|Altera "ModelSim ALTERA Starter Edition"]] for Windows and Linux.
    *[[http://en.wikipedia.org/wiki/Mentor_Graphics|EN.Wikipedia "Mentor Graphics"]], [[http://de.wikipedia.org/wiki/Mentor_Graphics|DE.Wikipedia "Mentor Graphics"]].
  *[[http://www.symphonyeda.com/|Symphony EDA "VHDL Simili"]] for Windows. 
    *[[http://www.symphonyeda.com/editions.htm|Symphony EDA "VHDL Simili" Editions]].
    *"FREE edition: The download ships with a default license file to enable the FREE edition... This FREE license file that ships with Version 3.1 expires on October 1 2012".

===== Code Coverage Tools & Lint Checkers for VHDL, Verilog =====
  *[[http://covered.sourceforge.net/|SourceForge "Covered - Verilog Code Coverage Analyzer"]], [[http://www.sourceforge.net/projects/covered|SourceForge "Covered"]].
  *[[http://www.vlsi-world.com/|VLSI World]].
    *[[http://www.vlsi-world.com/content/view/45/47/|VLSI World "Lint check"]] - list of commercial LINT tools for VHSL.
   *Commercial Lint tools.
    *Novas "nLint".
    *Synopsys "Leda".
    *[[http://www.cadence.com/|Cadence]] "Blacktie".
    *Atrenta "Spyglass".
===== Online Services for VHDL Development =====
==== EDA Playground ====
  *[[http://www.edaplayground.com/|EDA Playground]] by [[http://www.doulos.com/|Doulos]].
    *Use of Licensed Products within EDA Playground:
      -Aldec Riviera-PRO.
      -Cadence Xcelium.
      -Cadence Specman.
      -Mentor Precision.
      -Mentor Questa.
      -Synopsys VCS.
    *"To prevent your validation from being disabled, please supply your company or institution email address. Access will not be granted to freely available email addresses or to employees of rival tool vendors".
    *Suggestion: use "edaplayground@<companyname>" as username for this registration.
==== eDiViDe - Online Services for VHDL Development ====
  *[[http://web.archive.org/web/20181025211217/http://www.edivide.eu/|Archive.org "eDiViDe"]] ( - 20218-10-25 ) - "An online learning platform for digital electronics and focusses on providing a real FPGA based lab environment to students".
  *[[http://www.inf.h-bonn-rhein-sieg.de/en/People/Professors/Ploeger.html|Paul G. Plöger]].
  *[[http://www2.inf.fh-brs.de/~psamar2s|Hochschule Bonn-Rhein-Sieg "psamar2s"]].
===== Literature =====
  *Andrew Moore: "FPGAs For Dummies, 2nd Intel Special Edition".
  *[[http://www.freecomputerbooks.com/FPGA-for-Dummies.html|FreeComputerBooks "Andrew Moore: FPGAs for Dummies (Intel and Altera Special Edition)"]].
  *[[http://www.amazon.de/exec/obidos/ASIN/0470054379/hemmerling-21|Steve Kilts "Advanced FPGA Design: Architecture, Implementation, and Optimization"]], 2007.
===== Hardware Description Language Resources =====
==== Continuous Assignment vs. Procedural Assignment ====
  *[[http://www.fpgatutorial.com/s|FPGA Tutorial]].
    *[[http://www.fpgatutorial.com/systemverilog-continuous-assignment/|FPGA Tutorial "Continuous Assignment and Combinational Logic in SystemVerilog"]].
    *[[http://www.fpgatutorial.com/verilog-continuous-assignment/|FPGA Tutorial "Using Continuous Assignment to Model Combinational Logic in Verilog"]].
  *[[http://www.reddit.com/r/FPGA/comments/av739x/when_to_use_continuous_vs_procedural_assignment/|reddit "r/FPGA" - "When to use continuous vs procedural assignment?"]].
  *[[http://www.sciencedirect.com/topics/computer-science/continuous-assignment|ScienceDirect "Continuous Assignment"]].
  *[[http://electronics.stackexchange.com/questions/613718/how-to-use-case-for-continuous-assignment|StackExchange "How to use case for continuous assignment?"]].
  *[[http://www.stackoverflow.com/questions/23687172/using-a-continous-assignment-in-a-verilog-procedure|StackOverflow "Using a continous assignment in a Verilog procedure?"]].
==== General ====
  *[[http://www.fpgatutorial.com/s|FPGA Tutorial]].
  *[[http://tams-www.informatik.uni-hamburg.de/vhdl/|The Hamburg VHDL Archive]] - "We intend to provide a collection of free, i.e. public-domain or shareware, VHDL documentation, models, and tools".
  *[[http://www.opencores.org/|OpenCores]] - "#1 community within open source hardware IP-cores".
  *[[http://www.plc2.com/|PLC2 Programmable Logic Competence Center GmbH]].
    *The commercial conference  [[http://www.plc2.com/campus-days|ALL PROGRAMMABLE Campus Days]] with commercial trainings "Easy Start FPGA" ( with NEXYS3 Board ) and "Easy Start ZYNQ" ( with ZED Board ) in Osnabrück, 2013-11-05 - 2013-11-07.
    *[[http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS3|Digilent Inc. "Nexys3 Spartan-6 FPGA Board"]].
    *[[http://www.zedboard.org/|Zedboard.org]].
  *[[http://www.asic-world.com/|Deepak Kumar Tala "WELCOME TO WORLD OF ASIC"]] - "Tutorials, Examples, Tools, Books, Links" for VHDL, Verilog, SystemC, PSL as well as VERA and Specman #.
  *[[http://www.verilog.net/|Verilog.Net - "When fishing for Verilog information, don't forget the Net"]].


===== Appropriate OpenDirectory Directory Pages =====
  *[[http://www.dmoz.org/Business/Electronics_and_Electrical/|OpenDirectory "Top: Business: Electronics and Electrical"]].
  *[[http://www.dmoz.org/Science/Technology/Electronics/|OpenDirectory "Top: Science: Technology: Electronics"]].
  *[[http://www.dmoz.org/Science/Technology/Electronics/CAD/|OpenDirectory "Top: Science: Technology: Electronics: CAD"]].
  *[[http://www.dmoz.org/World/Deutsch/Wirtschaft/Elektrotechnik_und_Elektronik/|OpenDirectory "Top: World: Deutsch: Wirtschaft: Elektrotechnik und Elektronik"]].
  *[[http://www.dmoz.org/World/Deutsch/Wissenschaft/Ingenieurwissenschaften/Elektronik/|OpenDirectory "Top: World: Deutsch: Wissenschaft: Ingenieurwissenschaften: Elektronik"]].
  *[[http://dir.yahoo.com/business_and_economy/business_to_business/computers/software/cad_cam/ic_design/|Yahoo! Directory "B2B: CAD/CAM Software: IC Design"]].
  *[[http://dir.yahoo.com/business_and_economy/business_to_business/electronics/|Yahoo! Directory "Business and Economy: Business to Business: Electronics"]].
  *[[http://dir.yahoo.com/science/computer_science/electronic_computer_aided_design__ecad_/|Yahoo! Directory "Science: Computer Science: Electronic Computer Aided Design (ECAD)"]].
  *[[http://dir.yahoo.com/science/engineering/electrical_engineering/|Yahoo! Directory "Science: Engineering: Electrical Engineering"]].
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{{tag>"chip design"}}